A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having an interlayer insulating film made of insulating material having a dielectric constant lower than silicon oxide film, and to its manufacture method.
B) Description of the Related Art
FIG. 4 is a cross sectional view of a semiconductor device having a conventional multilevel wiring structure. Active regions are defined by an element separation insulating film 101 formed on the surface of a silicon substrate 100. A MOSFET 102 is formed in and above the active region, having a source region 102S, a drain region 102D and a gate electrode 102G.
Covering MOSFET 102, a via layer insulating film 103 made of a phosphorous silicate glass (PSG) is formed on the silicon substrate 100. The via layer insulating film 103 is formed by depositing a PSG film having a thickness of 1.5 μm by chemical vapor deposition (CVD) at a substrate temperature of 600° C. and thereafter planarizing the surface of the PSG film by chemical mechanical polishing (CMP).
On the via contact layer insulating film (via layer insulating film) 103, a protective film 104 is formed having a thickness of 50 nm and made of silicon nitride. A via hole 105 is formed extending through the protective film 104 and via layer insulating film 103 and reaching the surface of the drain region 102D. The bottom and inner wall of the via hole are covered with a barrier metal layer 107 of TiN or the like, and a tungsten (W) plug 106 is filled in the via hole 105.
On the protective film 104, a wiring layer insulating film 110 made of porous silica and having a thickness of 150 nm and a cap film 111 made of silicon oxide and having a thickness of 100 nm are formed in this order. A wiring trench 112 is formed through the two films, the wiring layer insulating film 110 and cap film 111. The bottom and inner wall of the wiring trench 112 are covered with a barrier metal layer 113 made of TaN. A first-layer copper wiring pattern 114 is filled in the wiring trench 112.
An etching stopper film 120 of silicon nitride having a thickness of 50 nm, a via layer insulating film 121 of porous silica having a thickness of 250 nm, an etching stopper film 122 of silicon nitride having a thickness of 50 nm, a wiring layer insulating film 123 of porous silica having a thickness of 150 nm and a cap film 124 of silicon oxide having a thickness of 100 nm are stacked in this order on the cap film 111 and copper wiring pattern 114.
A wiring trench 128 is formed extending from the upper surface of the cap film 124 to the bottom of the wiring layer insulating film 123, and a via hole 127 is formed extending from the bottom of the wiring trench 128 to the upper surface of the lower-level wiring pattern 114. The bottoms and inner walls of the via hole 127 and wiring trench 128 are covered with a barrier metal layer 129 of TaN. A second-layer copper wiring pattern 130 is buried in the via hole 127 and wiring trench 128.
In this conventional multilevel wiring structure shown in FIG. 4, the first-layer wiring insulating film 110, second-layer via layer insulating film 121 and wiring layer insulating film 123 are made of porous silica having a low dielectric constant. Parasitic capacitance between wiring patterns can therefore be reduced.
With this multilevel wiring structure shown in FIG. 4, however, the first-layer via layer insulating film 103 disposed between the first-layer wiring pattern 114 and silicon substrate 100 is made of PSG. The first-layer via layer insulating film 103 is not made of low dielectric constant material such as porous silica, because of preventing the electric characteristics of MOSFET 102 from being varied.
Since the first-layer via layer insulating film 103 is not made of low dielectric constant material, parasitic capacitance between the first-layer wiring pattern 114 and the conductive region formed in the surface layer of the silicon substrate 100 cannot be reduced. An electric field generated between wiring lines formed in the first-layer wiring layer insulating film 110 propagates in the underlying via layer insulating film 103. Therefore, the parasitic capacitance cannot be reduced although the via layer insulating film 110 is made of porous silica.